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* other brands and names are the property of their respective owners. information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. september 1994 copyright ? intel corporation, 1995 order number: 272267-004 8XC196NT chmos microcontroller with 1 mbyte linear address space y 20 mhz operation y high performance chmos 16-bit cpu y up to 32 kbytes of on-chip otprom y up to 1 kbyte of on-chip register ram y up to 512 bytes of internal ram y register-register architecture y 4 channel/10-bit a/d with sample/hold y 37 prioritized interrupt sources y up to seven 8-bit (56) i/o ports y full duplex serial i/o port y dedicated baud rate generator y interprocessor communication slave port y selectable bus timing modes for flexible external memory interfacing y oscillator fail detection circuitry y high speed peripheral transaction server (pts) y two dedicated 16-bit high-speed compare registers y 10 high speed capture/compare (epa) y full duplex synchronous serial i/o port (ssio) y two flexible 16-bit timer/counters y quadrature counting inputs y flexible 8-/16-bit external bus (programmable) y programmable bus (hold/hlda) y 1.4 m s 16 x 16 multiply y 2.4 m s 32/16 divide y 68-pin package device pins/package otprom reg code address i/o epa a/d ram ram space 8XC196NT 68p plcc 32k 1k 512 1 mbyte 56 10 4 x e 7 otprom device x e 0 romless the 8XC196NT 16-bit microcontroller is a high performance member of the mcs 96 microcontroller family. the 8XC196NT is an enhanced 8xc196kr device with 1 mbyte of linear address space, 1000 bytes of register ram, 512 bytes of internal ram, 20 mhz operation and an optional 32 kbytes of otprom. intel's chmos iii-e process provides a high performance processor along with low power consumption. ten high-speed capture/compare modules are provided. as capture modules event times with 200 ns resolu- tion can be recorded and generate interrupts. as compare modules events such as toggling of a port pin, starting an a/d conversion, pulse width modulation, and software timers can be generated. events can be based on the timer or up/down counter.
8XC196NT 272267 1 figure 1. 8XC196NT block diagram process information this device is manufactured on p629.5, a chmos iii-e process. additional process and reliability infor- mation is available in intel's components quality and reliability handbook , order number 210997. table 1. thermal characteristics package i ja i jc type plcc 36.5 c/w 13 c/w all thermal impedance data is approximate for static air conditions at 1w of power dissipation. values will change depending on operation conditions and ap- plication. see the intel packaging handbook (order number 240800) for a description of intel's thermal impedance test methodology. 272267 2 example: n87c196nt is 68-lead plcc otprom. for complete package dimensional data, refer to the intel packaging handbook (order number 240800). figure 2. the 8xc186nt familiy nomenclature 2
8XC196NT 8XC196NT memory map address description (note 7) ffffffh external memory ffa000h ff9fffh internal otprom or external memory (determined by ea pin) ff2080h reset at ff2080h ff207fh reserved memory (internal otprom or external memory) ff2000h (determined by ea pin) ff1fffh external memory ff0600h ff05ffh internal ram (identically mapped into 00400h 005ffh) ff0400h ff03ffh external memory ff0100h ff00ffh reserved for ice ff0000h feffffh external memory for future devices 100000h fffffh 984 kbytes external memory 00a000h 009fffh internal otprom or external memory (note 1) 002080h 00207fh reserved memory (internal otprom or external memory) 002000h (notes 1, 3, and 6) 001fffh memory mapped special function registers (sfr's) 001fe0h 001fdfh internal special function registers (sfr's) (note 5) 001f00h 001effh external memory 000600h 0005ffh internal ram 000400h (address with indirect or indexed modes) 0003ffh upper register file (address with indirect or register ram indexed modes or through windows.) (note 2) 000100h * 0000ffh register ram lower register file 000018h (address with direct, 000017h cpu sfr's indirect, or indexed 000000h * modes.) (notes 2, 4) notes: 1. these areas are mapped internal otprom if the remap bit (ccb2.2) is set and ea e 5v. otherwise they are external memory. 2. code executed in locations 00000h to 003ffh will be forced external. 3. reserved memory locations must contain 0ffh unless noted. 4. reserved sfr bit locations must be written with 0. 5. refer to 8XC196NT user's guide and quick reference for sfr descriptions. 6. warning: the contents or functions of reserved memory locations may change with future revisions of the device. therefore, a program that relies on one or more of these locations may not function properly. 7. the 8XC196NT internally uses 24 bit address, but only 20 address lines are bonded out allowing 1 mbyte external address space. 3
8XC196NT 272267 3 figure 3. 68-pin plcc package diagram 4
8XC196NT pin descriptions symbol name and function v cc main supply voltage ( a 5v). v ss ,v ss1 ,v ss1 digital circuit ground (0v). there are multiple v ss pins, all of which must be connected. v ref reference for the a/d converter ( a 5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. v pp programming voltage for the otprom parts. it should be a 12.5v for programming. it is also the timing pin for the return from powerdown circuit. connect to v cc if powerdown not being used. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . xtal1 input of the oscillator inverter and the internal clock generator. xtal2 output of the oscillator inverter. p2.7/clkout output of the internal clock generator. the frequency is (/2 the oscillator frequency. it has a 50% duty cycle. also lsio pin. reset reset input to and open-drain output from the chip. reset has an internal pullup. p5.7/buswidth input for bus width selection. if ccr bit 1 is a one and ccr1 bit 2 is a one, this pin dyamically controls the buswidth of the bus cycle in progress. if buswidth is low, an 8-bit cycle occurs, if buswidth is high, a 16-bit cycle occurs. if ccr bit 1 is ``0'' and ccr1 bit 2 is ``1'', all bus cycles are 8-bit, if ccr bit 1 is ``1'' and ccr1 bit 2 is ``0'', all bus cycles are 16-bit. ccr bit 1 e ``0'' and ccr1 bit 2 e ``0'' is illegal. also an lsio pin when not used as buswidth. nmi a positive transition causes a non maskable interrupt vector through memory location 203eh. p5.1/inst/slpcs output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is active only during external memory fetches, during internal otprom fetches inst is held low. also lsio when not inst. slpcs is the slave port chip select. ea input for memory select (external access). ea equal to a high causes memory accesses to locations 0ff2000h through 0ff9fffh to be directed to on-chip otprom. ea equal to a low causes accesses to these locations to be directed to off-chip memory. ea ea 12.5v causes execution to begin in the programming mode. ea is latched at reset. hold bus hold input requesting control of the bus. hlda bus hold acknowledge output indicating release of the bus. breq bus request output activated when the bus controller has a pending external memory cycle. p5.0/ale/adv / address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when slpaddr/ the pin is adv , it goes inactive (high) at the end of the bus cycle. adv can be used slpale as a chip select for external memory. ale/adv is active only during external memory accesses. also lsio when not used as ale. slpaddr is the slave port address control input and slpale is the slave port address latch enable input. p5.3/rd /slprd read signal output to external memory. rd is active only during external memory reads or lsio when not used as rd . slprd is the slave port read control input. 5
8XC196NT pin descriptions (continued) symbol name and function p5.2/wr /wrl /slpwr write and write low output to external memory, as selected by the ccr, wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is active during external memory writes. also an lsio pin when not used as wr /wrl . slpwr is the slave port write control input p5.5/bhe /wrh byte high enable or write high output, as selected by the ccr. bhe e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects that bank of memory that is connected to the low byte. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe e 1), to the high byte only (a0 e 1, bhe e 0) or both bytes (a0 e 0, bhe e 0). if the wrh function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe /wrh is only valid during 16-bit external memory read/write cycles. also an lsio pin when not bhe/wrh . p5.6/ready ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait state mode until the next positive transition in clkout occurs with ready high. when external memory is not used, ready has no effect. the max number of wait states inserted into the bus cycle is controlled by the ccr/ccr1. also an lsio pin when ready is not selected. p5.4/slpint dual function i/o pin. as a bidirectional port pin or as a system function. the system function is a slave port interrupt output pin. p6.2/t1clk dual function i/o pin. primary function is that of a bidirectional i/o pin, however, it may also be used as a timer1 clock input. the timer1 will increment or decrement on both positive and negative edges of this pin. p6.3/t1dir dual function i/o pin. primary function is that of a bidirectional i/o pin, however, it may also be used as a timer1 direction input. the timer1 will increment when this pin is high and decrements when this pin is low. port1/epa0 7 dual function i/o port pins. primary function is that of bidirectional i/o. system function is that of high speed capture and compare. epa0 and epa2 have yet p6.0 6.1/epa8 9 another function of t2clk and t2dir of the timer2 timer/counter. port 0/ach4 7 4-bit high impedance input-only port. these pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. these pins are also used as inputs to otprom parts to select the programming mode. p6.3 6.7/ssio dual function i/o ports that have a system function as synchronous serial i/o. two pins are clocks and two pins are data, providing full duplex capability. port 2 8-bit multi-functional port. all of its pins are shared with other functions. port 3 and 4 8-bit bidirectional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. eport 8-bit bidirectional standard and i/o port. these bits are shared with the extended address bus, a16 a19. pin function is selected on a per pin basis. intout interrupt output. this active-low output indicates that a pending interrupt requires use of the external bus. slp0 slp7 slave port address/data bus 6
8XC196NT absolute maximum ratings * storage temperature b 60 cto a 150 c voltage from v pp or ea to v ss or angnd b 0.5v to a 13.0v voltage from any other pin to v ss or angnd b 0.5 to a 7.0v this includes v pp on rom and cpu devices . power dissipation0.5w notice: this data sheet contains information on products in the sampling and initial production phases of development. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest data sheet be- fore finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions symbol parameter min max units t a ambient temperature under bias 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 4 20 mhz (note 4) note: angnd and v ss should be nominally at the same potential. dc characteristics (under listed operating conditions) symbol parameter min typ max units test conditions i cc v cc supply current 90 ma xtal1 e 20 mhz, v cc e v pp e v ref e 5.5v i ref a/d reference supply current 5 ma (while device in reset) i idle idle mode current 40 ma xtal1 e 20 mhz, v cc e v pp e v ref e 5.5v i pd powerdown mode current (6) 50 75 m av cc e v pp e v ref e 5.5v (11) v il input low voltage (all pins) b 0.5v 0.3 v cc v for port0 (10) v ih input high voltage 0.7 v cc v cc a 0.5 v for port0 (10) v ih1 input high voltage xtal1 0.7 v cc v cc a 0.5 v xtal1 input pin only (1) v ih2 input high voltage on reset 0.7 v cc v cc a 0.5 v reset input pin only v ol output low voltage 0.3 v i ol e 200 m a (3,5) (outputs configured as 0.45 v i ol e 3.2 ma complementary) 1.5 v i ol e 7.0 ma v oh output high voltage v cc b 0.3 v i oh eb 200 m a (3,5) (outputs configured as v cc b 0.7 v i oh eb 3.2 ma complementary) v cc b 1.5 v i oh eb 7.0 ma i li input leakage current (std. inputs) g 10 m av ss k v in k v cc i li1 input leakage current (port 0) g 3 m av cc k v in k v ref i il logical 0 input current b 70 m av in e 0.45v (1) 7
8XC196NT dc characteristics (under listed operating conditions) (continued) symbol parameter min typ max units test conditions v ol1 output low voltage in reset 0.8 v (note 7) v oh1 slpint (p5.4) and hlda (p2.6) 2.0 v i oh e 0.8 ma (7) output high voltage in reset v oh2 output high voltage in reset v cc b 1v v i oh eb 6 m a (1) c s pin capacitance (any pin to v ss )10pff test e 1.0 mhz r wpu weak pullup resistance 150k x (note 6) r rst reset pullup 65k 180k x notes: 1. all bd (bidirectional) pins except inst and clkout. inst and clkout are excluded due to their not being weakly pulled high in reset. bd pins include port1, port2, port3, port4, port5, port6 and eport except splint (p5.4) and hlda (p2.6). 2. standard input pins include xtal1, ea , reset, and port 1/2/5/6 and eport when setup as inputs. 3. all bidirectional i/o pins when configured as outputs (push/pull). 4. device is static and should operate below 1 hz, but only tested down to 4 mhz. 5. maximum i ol /i oh currents per pin will be characterized and published at a later date. 6. typicals are based on limited number of samples and are not guaranteed. the values listed are at room temperature and v ref e v cc e 5.5v. 7. violating these specifications in reset may cause the device to enter test modes (p5.4 and p2.6). 8. tbd e to be determined. 9. pullup present during return from powerdown condition. 10. when p0 is used as analog inputs, refer to a/d specifications. 11. for temperatures k 100 c typical is 10 m a. 8
8XC196NT 8XC196NT additional bus timing modes the 8XC196NT device has 3 additional bus timing modes for external memory interfacing. mode 3: mode 3 is the standard timing mode. use this mode for systems that emulate the 8xc196kr bus tim- ings. mode 0: mode 0 is the standard timing mode, but 1 (mini- mum) wait state is always inserted in external bus cycles. mode 1: mode 1 is the long r/w mode. this mode advances rd and wr signals by 1 t osc creatin ga2t osc rd /wr low time. ale is also advanced by 0.5 t osc but ale high time remains 1 t osc . mode 2: mode 2 is the long r/w mode with early address. mode 2 is similar to mode 1 with respect to rd ,wr , and ale signals. additionally, the address is output on the bus 0.5 t osc earlier in the bus cycle. 272267 4 figure 4. detailed mode 1, 2, 3, comparison 9
8XC196NT explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: signals: hehigh aeaddress haehlda lelow bebhe leale/adv vevalid brebreq qedata out xeno longer ceclkout rderd valid dedata wewr /wrh /wri zefloating gebuswidth xextal1 hehold yeready bus mode 0 and 3eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the system must meet these specifications to work with the 8XC196NT. symbol parameter min max units t avyv address valid to ready setup 2 t osc b 75 ns (3) t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (1) t avgv address valid to buswidth setup 2 t osc b 75 ns (2, 3) t llgv ale low to buswidth setup t osc b 60 ns (2, 3) t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 55 ns (2) t rldv rd active to input data valid t osc b 30 ns (2) t cldv clkout low to input data valid t osc b 60 ns t rhdz end of rd to input data float t osc ns t rhdx data hold after rd high 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc c n, where n e number of wait states. 3. if mode 0 is selected, one wait state minimum is always added. if additional wait states are required, add 2 t osc to the specification. 10
8XC196NT bus mode 0 and 3eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the 8XC196NT will meet these specifications symbol parameter min max units f xtal frequency on xtal1 4.0 20 mhz (1) t osc xtal1 period (1/f xtal ) 50 250 ns t xhch xtal1 high to clkout high or low a 20 110 ns t ofd clock failure to reset pulled low (6) 440 m s t clcl clkout period 2 t osc ns t chcl clkout high period t osc b 10 t osc a 30 ns t cllh clkout low to ale/adv high b 10 a 15 ns t llch ale/adv low to clkout high b 25 a 15 ns t lhlh ale/adv cycle time 4 t osc ns (5) t lhll ale/adv high time t osc b 10 t osc a 10 ns t avll address valid to ale low t osc b 15 ns t llax address hold after ale/adv low t osc b 40 ns t llrl ale/adv low to rd low t osc b 40 ns t rlcl rd low to clkout low b 5 a 35 ns t rlrh rd low period t osc b 5ns (5) t rhlh rd high to ale/adv high t osc t osc a 25 ns (3) t rlaz rd low to address float a 5ns t llwl ale/adv low to wr low t osc b 10 ns t clwl clkout low to wr low b 10 a 25 ns t qvwh data valid before wr high t osc b 23 ns t chwh clkout high to wr high b 10 a 15 ns t wlwh wr low period t osc b 30 ns (5) t whqx data hold after wr high t osc b 35 ns t whlh wr high to ale/adv high t osc b 10 t osc a 15 ns (3) t whbx bhe , inst hold after wr high t osc b 10 ns t whax ad8 15 hold after wr high t osc b 30 ns (4) t rhbx bhe , inst hold after rd high t osc b 10 ns t rhax ad8 15 hold after rd high t osc b 30 ns (4) notes: 1. testing performed at 8.0 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2 t osc c n, where n e number of wait states. if mode 0 (1 automatic wait state added) operation is selected, add 2 t osc to specification. 6. t ofd is the time for the oscillator fail detect circuit (ofd) to react to a clock failure. the ofd circuitry is enabled by programming the uprom location 0778h with the value 0004h. nt/nq customer qrom codes need to equate location 2016h to the value 0cdeh if the oscillator fail detect (ofd) function is desired. intel manufacturing uses location 2016h as a flag to determine whether or not to program the clock detect enable (cde) bit. programming the cde bit enables oscillator fail detection. 11
8XC196NT bus mode 0 and 3e8XC196NT system bus timing 272267 5 * if mode 0 operation is selected, add 2 t osc to this time. 12
8XC196NT 8XC196NT mode 0 and 3eready timings (one wait state) 272267 6 * if mode 0 selected, one wait state is always added. if additional wait states are required, add 2 t osc to these specifica- tions. mode 0 and 3e8XC196NT buswidth timings 272267 7 * if mode 0 selected, add 2 t osc to these specifications. 13
8XC196NT bus mode 1eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the system must meet these specifications to work with the 8XC196NT. symbol parameter min max units t avyv address valid to ready setup 2 t osc b 75 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (1) t avgv address valid to buswidth setup 2 t osc b 75 ns t llgv ale low to buswidth setup 1.5 t osc b 60 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3 t osc b 60 ns (2) t rldv rd active to input data valid 2 t osc b 44 ns (2) t cldv clkout low to input data valid t osc b 60 ns t rhdz end of rd to input data float t osc ns t rhdx data hold after rd high 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc c n, where n e number of wait states. 14
8XC196NT bus mode 1eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the 8XC196NT will meet these specifications symbol parameter min max units f xtal frequency on xtal1 8.0 20 mhz (1) t osc xtal1 period (1/f xtal ) 50 125 ns t xhch xtal1 high to clkout high or low a 20 110 ns t clcl clkout period 2 t osc ns t chcl clkout high period t osc b 10 t osc a 27 ns t chlh clkout high to ale/adv high 0.5 t osc b 15 0.5 t osc a 15 ns t clll clkout low to ale/adv low 0.5 t osc b 25 0.5 t osc a 15 ns t lhlh ale/adv cycle time 4 t osc ns (5) t lhll ale/adv high time t osc b 20 t osc a 10 ns t avll address valid to ale low 0.5 t osc b 20 ns t llax address hold after ale/adv low 0.5 t osc b 25 ns t llrl ale/adv low to rd low 0.5 t osc b 15 ns t rlcl rd low to clkout low t osc b 10 t osc a 30 ns t rlrh rd low period 2 t osc b 20 ns (5) t rhlh rd high to ale/adv high 0.5 t osc 0.5 t osc a 25 ns (3) t rlaz rd low to address float a 5ns t llwl ale/adv low to wr low 0.5 t osc b 10 ns t clwl clkout low to wr low t osc b 15 t osc a 25 ns t qvwh data valid before wr high 2 t osc b 23 ns t chwh clkout high to wr high b 10 a 15 ns t wlwh wr low period 2 t osc b 15 ns (5) t whqx data hold after wr high 0.5 t osc b 12 ns t whlh wr high to ale/adv high 0.5 t osc b 10 0.5 t osc a 15 ns (3) t whbx bhe hold after wr high t osc b 15 ns t whix inst hold after wr high 0.5 t osc b 15 t whax ad8 15 hold after wr high 0.5 t osc b 30 ns (4) t rhbx bhe hold after rd high t osc b 32 ns t rhix inst hold after rd high 0.5 t osc b 32 t rhax ad8 15 hold after rd high 0.5 t osc b 30 ns (4) notes: 1. testing performed at 8.0 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2 t osc c n, where n e number of wait states. 15
8XC196NT mode 1e8XC196NT system bus timing 272267 8 16
8XC196NT mode 1e8XC196NT ready timings (one wait state) 272267 9 mode 1e8XC196NT buswidth timings 272267 10 17
8XC196NT bus mode 2eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the system must meet these specifications to work with the 8XC196NT. symbol parameter min max units t avyv address valid to ready setup 2.5 t osc b 75 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (1) t avgv address valid to buswidth setup 2.5 t osc b 75 ns t llgv ale low to buswidth setup 1.5 t osc b 60 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid 3.5 t osc b 55 ns (2) t rldv rd active to input data valid 2 t osc b 44 ns (2) t cldv clkout low to input data valid t osc b 60 ns t rhdz end of rd to input data float 0.5 t osc ns t rhdx data hold after rd high 0 ns notes: 1. if max is exceeded, additional wait states will occur. 2. if wait states are used, add 2 t osc c n, where n e number of wait states. 18
8XC196NT bus mode 2eac characteristics (over specified operating conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. the 8XC196NT will meet these specifications symbol parameter min max units f xtal frequency on xtal1 8.0 20 mhz (1) t osc xtal1 period (1/f xtal ) 50 125 ns t xhch xtal1 high to clkout high or low a 20 a 85 ns t clcl clkout period 2 t osc ns t chcl clkout high period t osc b 10 t osc a 27 ns t chlh clkout high to ale/adv high 0.5 t osc b 15 0.5 t osc a 15 ns t clll clkout low to ale/adv low 0.5 t osc b 25 0.5 t osc a 15 ns t lhlh ale/adv cycle time 4 t osc ns (5) t lhll ale/adv high time t osc b 20 t osc a 10 ns t avll address valid to ale low t osc b 15 ns t llax address hold after ale/adv low 0.5 t osc b 20 ns t llrl ale/adv low to rd low 0.5 t osc b 15 ns t rlcl rd low to clkout low t osc b 10 t osc a 30 ns t rlrh rd low period 2 t osc b 20 ns (5) t rhlh rd high to ale/adv high 0.5 t osc b 5 0.5 t osc a 25 ns (3) t rlaz rd low to address float a 5ns t llwl ale/adv low to wr low 0.5 t osc b 10 ns t clwl clkout low to wr low t osc b 22 t osc a 25 ns t qvwh data valid before wr high 2 t osc b 25 ns t chwh clkout high to wr high b 10 a 15 ns t wlwh wr low period 2 t osc b 20 ns (5) t whqx data hold after wr high 0.5 t osc b 12 ns t whlh wr high to ale/adv high 0.5 t osc b 10 0.5 t osc a 10 ns (3) t whbx bhe hold after wr high t osc b 15 ns t whix inst hold after wr high 0.5 t osc b 15 t whax ad8 15 hold after wr high 0.5 t osc b 30 ns (4) t rhbx bhe hold after rd high t osc b 32 ns t rhix inst hold after rd high 0.5 t osc b 32 t rhax ad8 15 hold after rd high 0.5 t osc b 30 ns (4) notes: 1. testing performed at 8.0 mhz, however, the device is static by design and will typically operate below 1 hz. 2. typical specifications, not guaranteed. 3. assuming back-to-back bus cycles. 4. 8-bit bus only. 5. if wait states are used, add 2 t osc c n, where n e number of wait states. 19
8XC196NT mode 2e8XC196NT system bus timing 272267 11 20
8XC196NT mode 2e8XC196NT ready timings (one wait state) 272267 12 mode 2e8XC196NT buswidth timings 272267 13 21
8XC196NT bus mode 0, 1, 2, and 3ehold /hlda timings (over specified operation conditions) test conditions: capacitance load on all pins e 100 pf, rise and fall times e 10 ns. symbol parameter min max units t hvch hold setup time a 65 ns (1) t clhal clkout low to hlda low b 15 a 15 ns t clbrl clkout low to breq low b 15 a 15 ns t halaz hlda low to address float a 25 ns t halbz hlda low to bhe , inst, rd ,wr weakly driven a 25 ns t clhah clkout low to hlda high b 25 a 15 ns t clbrh clkout low to breq high b 25 a 25 ns t hahax hlda high to address no longer float b 15 ns t hahbv hlda high to bhe , inst, rd ,wr valid b 10 ns note: 1. to guarantee recognition at next clock. 8XC196NT hold /hlda timings 272267 14 22
8XC196NT ac characteristicseslave port slave port waveforme(slpl e 0) 272267 15 slave port timinge(slpl e 0) symbol parameter min max units t savwl address valid to wr low 50 ns t srhav rd high to address valid 60 ns t srlrh rd low period t osc ns t swlwh wr low period t osc ns t srldv rd low to output data valid 60 ns t sdvwh input data setup to wr high 20 ns t swhqx wr high to data invalid 30 ns t srhdz rd high to data float 15 ns notes: 1. test conditions: f osc e 20 mhz, t osc e 50 ns. rise/fall time e 10 ns. capacitive pin load e 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. 23
8XC196NT ac characteristicseslave port (continued) slave port waveforme(slpl e 1) 272267 16 slave port timinge(slpl e 1) symbol parameter min max units t selll cs low to ale low 20 ns t srheh rd or wr high to cs high 60 ns t sllrl ale low to rd low t osc ns t srlrh rd low period t osc ns t swlwh wr low period t osc ns t savll address valid to ale low 20 ns t sllax ale low to address invalid 20 ns t srldv rd low to output data valid 60 ns t sdvwh input data setup to wr high 20 ns t swhqx wr high to data invalid 30 ns t srhdz rd high to data float 15 ns notes: 1. test conditions: f osc e 20 mhz, t osc e 50 ns. rise/fall time e 10 ns. capacitive pin load e 100 pf. 2. these values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. specifications above are advanced information and are subject to change. 24
8XC196NT external clock drive symbol parameter min max units 1/t xlxl oscillator frequency 4 20 mhz t xlxl oscillator period (t osc ) 50 250 ns t xhxx high time 0.35 c t osc 0.65 t osc ns t xlxx low time 0.35 c t osc 0.65 t osc ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive waveforms 272267 17 ac testing input, output waveforms 272267 18 ac testing inputs are driven at 3.5v for a logic ``1'' and 0.45v for a logic ``0''. timing measurements are made at 2.0v for a logic ``1'' and 0.8v for logic ``0''. float waveforms 272267 19 for timing purposes a port pin is no longer floating when a 150 mv change from load voltage occurs and begins to float when a 150 mv change from the loading v oh /v ol level occurs i ol /i oh s 15 ma. 25
8XC196NT waveformeserial porteshift register mode serial port waveformeshift register mode (mode 0) 272267 20 ac characteristicseserial port-shift register mode serial port timingeshift register mode (mode 0) test conditions: t a eb 40 cto a 125 c; v cc e 5.0v g 10%; v ss e 0.0v; load capacitance e pf symbol parameter min max units t xlxl (2) serial port clock period (brr t 8002h) receive only 6 t osc ns t xlxh (2) serial port clock falling edge to rising edge (brr t 8002h) 4 t osc b 50 4 t osc a 50 ns t xlxl (2) serial port clock period (brr e 8001h) transmit only 4 t osc ns t xlxh (2) serial port clock falling edge to rising edge (brr e 8001h) 2 t osc b 50 2 t osc a 50 ns t qvxh output data setup to clock rising edge 3 t osc ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge 2 t osc a 200 ns t xhdx (1) input data hold after clock rising edge 0 ns t xhqz (1) last clock rising to output float 5 t osc ns notes: 1. parameters not tested. 2. the minimum baud rate register value for receive is 8002h. the minimum baud rate register value for transmit is 8001h. 26
8XC196NT a to d characteristics the a/d converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of v ref . 10-bit mode a/d operating conditions symbol description min max units t a ambient temperature 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v (1) t sam sample time 1.0 m s (2) t conv conversion time 10 15 m s (2) f osc oscillator frequency 4.0 20 mhz notes: 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 10-bit mode a/d characteristics (using above operating conditions) (6) parameter typ * (1) min max units * resolution 1024 1024 level 10 10 bits absolute error 0 g 3.0 lsbs full scale error 0.25 g 0.5 lsbs zero offset error 0.25 g 0.5 lsbs non-linearity 1.0 g 2.0 g 3.0 lsbs differential non-linearity b 0.75 a 0.75 lsbs channel-to-channel matching g 0.1 0 g 1.0 lsbs repeatability g 0.25 0 lsbs (1) temperature coefficients: offset 0.009 lsb/c (1) full scale 0.009 lsb/c (1) differential non-linearity 0.009 lsb/c (1) off isolation b 60 db (1,2,3) feedthrough b 60 db (1,2) v cc power supply rejection b 60 db (1,2) input resistance 750 1.2k x (4) dc input leakage g 1.0 0 g 3.0 m a voltage on analog input pin angnd b 0.5 v ref a 0.5 v (5) sampling capacitor 3.0 pf * an ``lsb'' as used here has a value of approximately 5 mv. notes: 1. these values are expected for most parts at 25 c, but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. applying voltages beyond these specifications will degrade the accuracy of other channels being converted. 6. all conversions performed with processor in idle mode. 27
8XC196NT 8-bit mode a/d operating conditions symbol description min max units t a ambient temperature 0 a 70 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v (1) t sam sample time 1.0 m s (2) t conv conversion time 7 20 m s (2) f osc oscillator frequency 4.0 20 mhz notes: 1. v ref must be within 0.5v of v cc . 2. the value of ad e time is selected to meet these specifications. 8-bit mode a/d characteristics (using above operating conditions) (6) parameter typ * (1) min max units * resolution 256 256 level 8 8 bits absolute error 0 g 1.0 lsbs full scale error g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 1.0 lsbs differential non-linearity b 0.5 a 0.5 lsbs channel-to-channel matching 0 g 1.0 lsbs repeatability g 0.25 0 lsbs (1) temperature coefficients: offset 0.003 lsb/c (1) full scale 0.003 lsb/c (1) differential non-linearity 0.003 lsb/c (1) off isolation b 60 db (1,2,3) feedthrough b 60 db (1,2) v cc power supply rejection b 60 db (1,2) input resistance 750 1.2k x (4) dc input leakage g 1.0 0 g 3.0 m a voltage on analog input pin angnd b 0.5 v ref a 0.5 v (5) sampling capacitor 3.0 pf * an ``lsb'' as used here has a value of approximately 5 mv. notes: 1. these values are expected for most parts at 25 c, but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make is guaranteed. 4. resistance from device pin, through internal mux, to sample capacitor. 5. applying voltage beyond these specifications will degrade the accuracy of other channels being converted. 6. all conversions performed with processor in idle mode. 28
8XC196NT otprom specifications operating conditions symbol description min max units t a ambient temperature during programming 20 30 c v cc supply voltage during programming 4.5 5.5 v (1) v ref reference supply voltage during programming 4.5 5.5 v (1) v pp programming voltage 12.25 12.75 v (2) v ea ea pin voltage 12.25 12.75 v (2) f osc oscillator frequency during auto 6.0 8.0 mhz and slave mode programming f osc oscillator frequency during 6.0 20.0 mhz run-time programming notes: 1. v cc and v ref should nominally be at the same voltage during programming. 2. v pp and v ea must never exceed the maximum specification, or the device may be damaged. 3. v ss and angnd should nominally be at the same potential (0v). 4. load capacitance during auto and slave mode programming e 150 pf. ac otprom programming characteristics (slave mode) symbol parameter min max units t avll address setup time 0 t osc t llax address hold time 100 t osc t dvpl data setup time 0 t osc t pldx data hold time 400 t osc t lllh pale pulse width 50 t osc t plph prog pulse width (2) 50 t osc t lhpl pale high to prog low 220 t osc t phll prog high to next pale low 220 t osc t phdx word dump hold time 50 t osc t phpl prog high to next prog low 220 t osc t lhpl pale high to prog low 220 t osc t pldv prog low to word dump valid 50 t osc t shll reset high to first pale low 1100 t osc t phil prog high to ainc low 0 t osc t ilih ainc pulse width 240 t osc t ilvh pver hold after ainc low 50 t osc t ilpl ainc low to prog low 170 t osc t phvl prog high to pver valid 220 t osc notes: 1. run-time programming is done with f osc e 6.0 mhz to 10.0 mhz, v cc ,v pd ,v ref e 5v g 0.5v, t c e 25 c g 5 c and v pp e 12.5v g 0.25v. for run-time programming over a full operating range, contact factory. 2. this specification is for the word dump mode. for programming pulses use modified quick pulse algorithm. 29
8XC196NT dc otprom programming characteristics symbol parameter min max units i pp v pp programming supply current 200 ma note: do not apply v pp unti v cc is stable and within specifications and the oscillator/clock has stabilized or the device may be damaged. otprom programming waveforms slave programming mode data program mode with single program pulse 272267 21 note: p3.0 must be high (``1'') slave programming mode in word dump mode with auto increment 272267 22 note: p3.0 must be low (``0'') 30
8XC196NT slave programming mode timing in data program mode with repeated prog pulse and auto increment 272267 23 this data sheet (272267-004) applies to devices marked with a ``d'' at the end of the top side tracking number. 8XC196NT design considerations 1. when operating in bus timing modes 1 or 2, the upper and lower address/data lines must be latched. even in 8-bit bus mode, the upper ad- dress lines must be latched. in modes 0 and 3, the upper address lines do not need to be latched in 8-bit bus width mode. but in 16-bit buswidth mode the upper address lines need to be latched. 8XC196NT errata see faxback y 2344 1. illegal opcode interrupt vector. 2. aborted interrupt vectors to lowest priority. 3. pts request during interrupt latency. data sheet revision history this datasheet applies to devices marked with a ``d'' at the end of the topside tracking number. the top- side tracking number consists of nine characters and is the second line on the top side of the device. datasheets are changed as new device information becomes available. verify with your local intel sales office that you have the latest version before finaliz- ing a design or ordering devices. the following are differences between the 272267- 003 and 272267-004 datasheets: 1. changed all references of ``eprom'' to ``otprom''. 2. added all the slave port pins to the package diagram and pin descriptions. 3. added intout pin to pin descriptions. 4. changed ili1 (input leakage current for port 0) from g 1 m ato g 3 m a. 5. removed t llyv from ac characterisics and waveform diagrams. 6. t rlcl in mode 0 and 3, changed from a 4ns min. to b 5 ns min. 7. t whqx in mode 0 and 3, changed from t osc b 30 min. to t osc b 35 min. 8. clarified the ready waveform timings for mode 0 and 3, by adding `` a 2t osc * ''. 9. t lhll in mode 1, changed from t osc b 10 min. to t osc b 20 min. 10. t avll in mode 1, changed from 0.5 t osc b 15 min. to 0.5 t osc b 20 min. 11. t llax in mode 1, changed from 0.5 t osc b 20 min. to 0.5 t osc b 25 min. 12. t lhll in mode 2, changed from t osc b 10 min. to t osc b 20 min. 13. t xlxl and t xlxh for the serial port timings were changed to reflect the minimum baudrate for receive and transmit modes. 14. added the 8XC196NT errata section. 31

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